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1
TC826 A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT
FEATURES
s s s s s s s s s s s s s s s s Bipolar A/D Conversion 2.5% Resolution Direct LCD Display Drive `Thermometer' Bar or Dot Display 40 Data Segments Plus Zero Overrange Plus Polarity Indication Precision On-Chip Reference ................ 35ppm/C Differential Analog Input Low Input Leakage .......................................... 10pA Display Flashes on Overrange Display Hold Mode Auto-Zero Cycle Eliminates Zero Adjust Potentiometer 9V Battery Operation Low Power Consumption ............................ 1.1mW 20mV to 2.0 V Full-Scale Operation Non-Multiplexed LCD Drive for Maximum Viewing Angle
2 3 4 5 6 7
Temperature 0C to +70C
GENERAL DESCRIPTION
In many applications a graphical display is preferred over a digital display. Knowing a process or system operates, for example, within design limits is more valuable than a direct system variable readout. A bar or moving dot display supplies information precisely without requiring further interpretation by the viewer. The TC826 is a complete analog-to-digital converter with direct liquid crystal (LCD) display drive. The 40 LCD data segments plus zero driver give a 2.5% resolution bar display. Full-scale differential input voltage range extends from 20mV to 2V. The TC826 sensitivity is 500v. A low drift 35 ppm/C internal reference, LCD backplane oscillator and driver, input polarity LCD driver, and overrange LCD driver make designs simple and low cost. The CMOS design required only 125A from a 9V battery. In +5V systems a TC7660 DC to DC converter can supply the -5V supply. The differential analog input leakage is a low 10pA. Two display formats are possible. The BAR mode display is like a `thermometer' scale. The LCD segment driver that equals the input plus all below it are on. The DOT mode activates only the segment equal to the input. In either mode the polarity signal is active for negative input signals. An overrange input signal causes the display to flash and activates the overrange annunciator. A hold mode can be selected that freezes the display and prevents updating. The dual slope integrating conversion method with auto-zero phase maximizes noise immunity and eliminates zero-scale adjustment potentiometers. Zero-scale drift is a low 5 V/C. Conversion rate is typically 5 per second and is adjustable by a single external resistor. A compact, 0.5" square, flat package minimizes PC board area. The high pin count LSI package makes multiplexed LCD displays unnecessary. Low cost, direct drive LCD displays offer the widest viewing angle and are readily available. A standard display is available now for TC826 prototyping work.
PIN CONFIGURATION
BAR/DOT BAR 40 BAR 39 BAR 38 BAR 37 BAR 36 BAR 35 BAR 33 BAR 32 50 BAR 34 BAR 31 49 48 47 46 45 44 43 42 41 NC BAR 30 BAR 29 BAR 28 BAR 27 BAR 26 BAR 25 BAR 24 BAR 23 BAR 22 BAR 21 BAR 20 BAR 19 BAR 18 BAR 17 BAR 16 40 39 38 37 36 35 34 33 17 NC 18 BAR 1 19 BAR 2 20 BAR 3 21 BAR 4 22 BAR 5 23 BAR 6 24 BAR 7 25 BAR 8 26 BAR 9 27 BAR 10 28 BAR 11 29 BAR 12 30 BAR 13 31 BAR 14 32 BAR 15 POL - 60 HOLD TEST
64 NC ANALOG COMMON +IN - IN REF IN + CREF - CREF VDD VBUF CAZ VINT VSS OSC1 OSC2 BP BAR 0 1 2 3 4 5 6 7 8
NC
63
62
61
59
OR
58
57
56
55
54
53
52
51
TC826CBU
9 10 11 12 13 14 15 16
ORDERING INFORMATION
Part No. TC826CBU Package 64-Pin PFP
8
TC826-6 11/6/96
TELCOM SEMICONDUCTOR, INC.
3-171
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V-) ............................................ 15V Analog Input Voltage (either input)(1) ................... V+ to V- Power Dissipation (TA 70C) 64-Pin Flat Package .........................................1.14W Operating Temperature `C' Devices ............................................. 0C to +70C Storage Temperature ............................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C
*Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS: unless otherwise stated VS = 9V; ROSC = 430 k; TA = 25C; Full-Scale = 20 mV.
No. Symbol
1 2 3 4 5 6 7 8 -- -- NL R/O EN ILK CMRR --
Parameter
Zero Input Zero Reading Drift Linearity Error Rollover Error Noise Input Leakage Current Common-Mode Rejection Ratio Scale Factor Temperature Coefficient Analog Common Temperature Coefficient Analog Common Voltage LCD Segment Drive Voltage LCD Backplane Drive Voltage Power Supply Current
Test Conditions
VIN = 0.0V VIN = 0.0V 0C TA +70C Max Deviation From Best Straight Line -VIN = +VIN VIN = 0V VIN = 0V VCM = 1V VIN = 0V 0 TA +70C External Ref. Temperature Coefficient = 0 ppm/C 250k Between Common and V+ 0C TA +70C 250k Between Common and VDD
Min
-0 -- -1 -1 -- -- -- --
Typ
0 0.2 0.5 0 60 10 50 1
Max
+0 1 +1 +1 -- 20 -- --
Unit
Display V/C Count Count VP-P pA V/V ppm/C
9
VCTC
--
35
100
ppm/C
10 11 12 13
VCOM VSD VBD IDD
2.7 4 4 --
2.9 5 5 125
3.35 6 6 175
V VP-P VP-P A
NOTES: 1. Input voltages may exceed the supply voltages when the input current is limited to 100A. 2. Static sensitive device. Unused devices should be stored in conductive material to protect devices from static discharge and static fields. 3. Backplane drive is in phase with segment drive for `off' segment and 180C out of phase for `on' segment. Frequency is 10 times conversion rate. 4. Logic input pins 58, 59, and 60 should be connected through 1M series resistors to VSS for logic 0.
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A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
PIN DESCRIPTION Pin No. (64-Plastic Quad Flat Package) Symbol
1 2 NC ANALOG COMMON +IN -IN REF IN CREF + CREF- VDD VBUF CAZ VINT VSS OSC1 OSC2 BP BAR 0 NC BAR 1 BAR 2 BAR 3 BAR 4 BAR 5 BAR 6 BAR 7 BAR 8 BAR 9 BAR 10 BAR 11 BAR 12 BAR 13 BAR 14 BAR 15 BAR 16 BAR 17 BAR 18 BAR 19 BAR 20 BAR 21 BAR 22 BAR 23
1
2
Description
Establishes the internal analog ground point. Analog common is set to 2.9V below the positive supply by an internal zener reference circuit. The voltage difference beween VDD and analog-common can be used to supply the TC826 voltage reference input at REF IN (Pin 5). Positive analog signal input. Negative analog signal input. Reference voltage positive input. Measured relative ato analog-common. REF IN Full-Scale/2. Reference capacitor connection. Reference capacitor connection. Positive supply terminal. Buffer output. Integration resistor connection. Negative comparator input. Auto-zero capacitor connection. Integrator output. Integration capacitor connection. Negative supply terminal. Oscillator resistor (ROSC) connection. Oscillator resistor (ROSC) connection. LCD Backplane driver. LCD Segment driver: Bar 0 LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: Bar 1 Bar 2 Bar 3 Bar 4 Bar 5 Bar 6 Bar 7 Bar 8 Bar 9 Bar 10 Bar 11 Bar 12 Bar 13 Bar 14 Bar 15 Bar 16 Bar 17 Bar 18 Bar 19 Bar 20 Bar 21 Bar 22 Bar 23
3-173
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3 4 5 6 7
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TELCOM SEMICONDUCTOR, INC.
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
PIN DESCRIPTION (Cont.)
Pin No. (64-Plastic Quad Flat Package) Symbol
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 BAR 24 BAR 25 BAR 26 BAR 27 BAR 28 BAR 29 BAR 30 NC BAR 31 BAR 32 BAR 33 BAR 34 BAR 35 BAR 36 BAR 37 BAR 38 BAR 39 BAR 40 OR POL-
Description
LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: LCD Segment driver: Bar 24 Bar 25 Bar 26 Bar 27 Bar 28 Bar 29 Bar 30
LCD Segment driver: Bar 31 LCD Segment driver: Bar 32 LCD Segment driver: Bar 33 LCD Segment driver: Bar 34 LCD Segment driver: Bar 35 LCD Segment driver: Bar 36 LCD Segment driver: Bar 37 LCD Segment driver: Bar 38 LCD Segment driver: Bar 39 LCD Segment driver: Bar 40 LCD segment driver that indicated input out-of-range condition. LCD segment driver that indicates input signal is negative. Input logic signal that selects bar or dot display format. Normally in bar mode. Connect to VSS through 1M resistor for Dot format. Input logic signal that prevents display from changing. Pulled high internally to inactive state. Connect to VSS through 1M series resistor for HOLD mode operation. Input logic signal. Sets TC826 to BAR display mode. BAR 0 to 40, plus OR flash on and off. The POL- LCD driver is on. Pulled high internally to inactive state. Connect to VSS with 1 M series resistor to activate.
64
NC
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A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
CINT
1
2
11 VINT + CREF - CREF OSC1 6 7 13 ROSC 430k OSC2 BP 14 15 59 CREF 1.0f
RINT 9 1M 61 VBUF BAR/DOT
CAZ 10 CAZ
1M
62
3 4
HOLD TC826
1M
63 12
TEST VSS VDD 8 REF IN 5 ANALOG COMMON -IN +IN 2 4 3
OR BAR0- BAR40 POL-
SEGMENT DRIVE
60 BACKPLANE
9V
R1
R2 -IN +IN
41 SEGMENT LCD BAR GRAPH - OR
COMPONENT RINT CINT CREF CAZ
2V 200 mV 20 mV FULL-SCALE FULL-SCALE FULL-SCALE 2M 0.033f 1f 0.068f 20k 0.033 f 1f 0.068f 20k 0.033 f 1f 0.014f R1 + R2 = 250k
5 6 7
Figure 1. Typical TC826 Circuit Connection
8
TELCOM SEMICONDUCTOR, INC.
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A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
DUAL SLOPE CONVERSION PRINCIPLES
The TC826 is a dual slope, integrating analog-to-digital converter. The conventional dual slope converter measurement cycle has two distinct phases: * Input Signal Integration * Reference Voltage Integration (Deintegration) The input signal being converted is integrated for a fixed time period (TSI). Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (TRI). (Figure 2). In a simple dual slope converter a complete conversion requires the integrator output to `ramp-up' and `ramp- down'. A simple mathematical equation relates the input signal reference voltage and integration time:
1 RC
The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Noise spikes are integrated or averaged to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. (Figure 3.) The TC826 converter improves the conventional dual slope conversion technique by incorporating an auto-zero phase. This phase eliminates zero-scale offset errors and drift. A potentiometer is not required to obtain a zero output for zero input.
NORMAL MODE REJECTION (dB)
30 T = MEASUREMENT PERIOD 20
TSI VI N (t) dt = 0
VR TR I RC
Where: VR = Reference Voltage VSI = Signal Integration Time (Fixed) TRI = Reference Voltage Integration Time (Variable) For a constant VIN: VI N = VR T
TR I
SI
10
0 0.1/T
1/T INPUT FREQUENCY
10/T
Figure 3. Normal-Mode Rejection of Dual Slope Converter
C INTEGRATOR
ANALOG INPUT SIGNAL +/-
R
- +
- +
COMPARATOR
REF VOLTAGE
SWITCH DRIVER POLARITY CONTROL
PHASE CONTROL CONTROL LOGIC CLOCK
INTEGRATOR OUTPUT
VIN 1/2 VFULL-SCALE VIN 1/4 VFULL-SCALE
COUNTER
FIXED SIGNAL VARIABLE INTEGRATE REFERENCE TIME INTEGRATE TIME
DISPLAY
Figure 2. Basic Dual Slope Converter 3-176
TELCOM SEMICONDUCTOR, INC.
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
THEORY OF OPERATION Analog Section
In addition to the basic signal integrate and deintegrate cycles discussed above, the TC826 incorporates an autozero cycle. This cycle removes buffer amplifier, integrator, and comparator offset voltage error terms from the conversion. A true digital zero reading results without external adjusting potentiometers. A complete conversion consists of three cycles: an auto-zero, signal integrate and reference cycle. (Figures 4 and 5.) Auto-Zero Cycle During the auto-zero cycle the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (internal analog ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator
REF IN CREF 5 6 7 9 CAZ 10 CINT 11
1
offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero cycle length is 19 counts minimum. Unused time in the deintegrate cycle is added to the autozero cycle. Signal Integration Cycle The auto-zero loop is opened and the internal differential inputs connect to +IN and -IN. The differential input signal is integrated for a fixed time period. The TC826 signal integration period is 20 clock periods or counts. The externally set clock frequency is divided by 32 before clocking the internal counters. The integration time period is: Where: TSI = 32 x 20 FOSC
2 3 4
FOSC = External Clock Frequency
RINT VDD 8
AZ INTEGRATOR
-
+ INPUT 3
- +
BUFFER
+ -
COMPARATOR
5
CMPTR TO DIGITAL SECTION
+
INT DE- DE+
AZ
AZ AZ ANALOG COMMON 2 DE+ DE-
INT VDD VDD
6
6.3V 1A
- INPUT
4
INT
FROM DIGITAL CONTROL SECTION
AZ INT DE+ DE-
VDD - 2.9V
- +
7
ANALOG SWITCH
TC826
12 VDD
Figure 4. TC826 Analog Section
8
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TELCOM SEMICONDUCTOR, INC.
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, -IN should be tied to analog-common. This is the usual connection for battery operated systems. Polarity is determined at the end of signal integrate signal phase. The sign bit is a true polarity indication in that signals less than 1 LSB are correctly determined. This allows precision null detection limited only by device noise and system noise. Reference Integrate Cycle The final phase is reference integrate or deintegrate. -IN is internally connected to analog common and +IN is connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 40 counts. The digital reading displayed is:
20 = VI N VREF
takes a total of 80 clock pulses. The 80 count cycle is independent of input signal magnitude. Each phase of the measurement cycle has the following length: * Auto-Zero Phase: 19 to 59 Counts For signals less than full-scale the auto-zero is assigned the unused reference integrate time period. * Signal Integrate: 20 Counts This time period is fixed. The integration period is: 32 TSI = 20 FOSC Where FOSC is the externally set clock frequency. * Reference Integrate: 0 to 41 Counts
Reference Voltage Selection
A full-scale reading requires the input signal be twice the reference voltage. The reference potential is measured between REF IN (Pin 5) and ANALOG COMMON Pin 2). Required Full-Scale Voltage 20mV 2V VREF 10mV 1V
System Timing
The oscillator frequency is divided by 32 prior to clocking the internal counters. The three phase measurement cycle
AUTO-ZERO PHASE (AZ)
SIGNAL INTEGRATE PHASE (SI)
REFERENCE INTEGRATE PHASE (RI) (DEINTEGRATE) SIGN BIT DETERMINED
INTEGRATOR OUTPUT
ANALOG COMMON POTENTIAL TRUE ZERO CROSSING INTERNAL SYSTEM CLOCK (FSYS) INTERNAL DATA LATCH UPDATE SIGNAL ZERO CROSSING DETECTED
TI 19 COUNTS MINIMUM 20 COUNTS
TD VIN
NUMBER OF COUNTS PROPORTIONAL TO VIN
41 COUNTS MAXIMUM 1 ONE CONVERSION CYCLE = 80 COUNTS ( TCONV = 80 X ) FSYS
Figure 5. TC826 Conversion Has Three Phases 3-178
TELCOM SEMICONDUCTOR, INC.
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
The internal voltage reference potential availabe at analog-common will normally be used to supply the converters reference. This potential is stable whenever the supply potential is greater than approximately 7V. In applications where an externally generated reference voltage is desired refer to Figure 6. The reference voltage is adjusted with a near full-scale input signal. Adjust for proper LCD display readout.
V+
1
Auto-Zero Capacitor (CAZ) CAZ should be 2-3 times larger than the integration capacitor. A polypropylene capacitor is suggested. Typical values from 0.14F to 0.068 F are satisfactory. Reference Capacitor (CREF) A 1 F capacitor is suggested. Low leakage capacitors such as polypropylene are recommended. Several capacitor/resistor combinations for common full-scale input conditions are given in Table 1. Table 1 Suggested Component Values
2 3 4 5 6 7
V
8 +
2V 200 mV 20 mV Full-Scale Full-Scale Full-Scale Component VREF 1V VREF 100 mV VREF 10 mV
5 2 TC9491CZM 1.2V REFERENCE
TC826 REF IN ANALOG COMMON (b)
RINT CINT CREF CAZ ROSC
2 M 0.033F 1F 0.068F 430k
200k 0.033F 1F 0.068F 430k
20k 0.033F 1F 0.14F 430k
NOTES: Approximately 5 conversions/second.
Figure 6. External Reference
Differential Signal Inputs
The TC826 is designed with true differential inputs and accepts input signals within the input stage common-mode voltage range (VCM). The typical range is V+ -1 to V- +1V. Common-mode voltages are removed from the system when the TC826 operates from a battery or floating power source (Isolated from measured system) and -IN is connected to analog-common (VCOM). In systems where common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. Integrator output saturation must be prevented. A worse case condition exists if a large positive VCM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output positive along with VCM. For such applications, the integrator output swing can be reduced below the recommended 2V full-scale swing. The integrator output will swing within 0.3V of VDD or VSS without increased linearity error.
Components Value Selection
Integrating Resistor (RINT) The desired full-scale input voltage and output current capability of the input buffer and integrator amplifier set the integration resistor value. The internal class A output stage amplifiers will supply a 1A drive durrent with minimal linearity error. RINT is easily calculated for a 1A full-scale current: RINT = Full-Scale Input Voltage (V) = VFS 1 x 10 -6 1 x10-6 Where VFS = Full-Scale Analog Input Integrating Capacitor (CINT) The integrating capacitor should be slected to maximize intgrator output swing. The integrator output will swing to within 0.4V of VS+ or VS- without saturating. The integrating capacitor is easily calculated: CINT = Where : VFS RINT
Digital Section
The TC826 contains all the segment drivers necessary to drive a liquid crystal display (LCD). An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 256. A 430k OSC gets the backplane frequency to approximately 55Hz with a 5V nominal amplitude. When a segment driver is in phase with the backplane signal the segment is `OFF'. An out-of-phase segment drive signal causes the segment to be `ON' or visible. This AC drive configuration results in negligible DC
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(F
640 OSC x VINT
)
VINT = Integrator Swing FOSC = Oscillator Frequency
The integrating capacitor should be selected for low dielectric absorption to prevent roll-over errors. Polypropylene capacitors are suggested. TELCOM SEMICONDUCTOR, INC.
8
A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
voltage across each LCD segment. This insures long LCD display life. The polarity segment drive, -POL, is `ON' for negative analog inputs. If +IN and -IN are reversed this indicator would reverse. The TC826 transfer function is shown in Figure 7.
OVERRANGE INDICATION
In the BAR display format the 41 bar segments and the overrange annunciator, OR, will flash ON and OFF. The flash rate is on fourth the conversion rate (FOSC/2560). In the DOT display mode, OR flashes and all other data segment drivers are off.
Polarity Indication (POL- Pin 60)
The TC826 converts and displays data for positive and negative input signals. The POL- LCD segment driver (Pin 60) is active for negative signals.
40
DIGITAL DISPLAY
39 2 1 -0.5 0
Oscillator Operation
The TC826 external oscillator frequency, FOSC, is set by resistor ROSC connected between pins 13 and 14. The oscillator frequency versus resistance curve is shown in Figure 8.
50 20 18 40 16 TA = 25C VDDTO VSS = 9V
-2
-1
0.5 1
2
3
39 39.5 40 40.5
ANALOG INPUT VFS ) (X 40
Figure 7. TC826 Transfer Function
BAR/DOT Input (Pin 61)
FOSC (kHz)
CONV (CONV/SEC)
14 12 10 8 6 4 2
The BAR/DOT input allows the user to select the display format. The TC826 powers up in the BAR mode. Select the DOT display format by connecting BAR/DOT to the negative supply (Pin 12) through a 1M resistor.
30
20
10
HOLD Input (Pin 62)
The TC826 data ouput latches are not updated at the end of each conversion if HOLD is tied to the negative supply (Pin 12) through a 1 M resistor. The LCD display continously displays the previous conversion results. The HOLD pin is normally pulled high by an internal pullup.
0
0 0
2
4
6 8 10 12 14 16 18 20 ROSC (X 100k)
Figure 8. Oscillator Frequency vs. ROSC
TEST Input (Pin 63)
The TC826 enters a test mode with the TEST input connected to the negative supply (Pin 12). The connection must be made through a 1M resistor. The TEST input is normally internally pulled high. A low input sets the output data latch to all ones. The BAR display mode is set. The 41 LCD output segments (zero plus 40 data segments) and overrange annuniciator flash on and off at 1/4 the conversion rate. The polarity annunciator (POL-) segment will be on but not flashing
FOSC is divided by 32 to provide an internal system clock, FYSY. Each conversion requires 80 internal clock cycles. The internal system clock is divided by 8 to provide the LCD backplane drive frequency. The display flash rate during an input out-of-range signal is set by dividing FSYS by 320. The internal oscillator may be bypassed by driving OSCI (Pin 13) with an external signal generator. OSC2 (Pin 14) should be left unconnected. The oscillator should swing from VDD to VSS in single supply operation (Figure 9). In dual supply operation the signal should swing from power supply ground to VDD.
Overrange Display Operation (OR, Pin 59)
An out-of-range input signal will be indicated on the LCD display by the OR annunciator driver (Pin 59) becoming active.
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A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
A. BAR MODE
8 TC826 9V
1
1. INPUT = 0 BAR 4
12 13 OSC1 14 OSC2
2. INPUT = 5% OF FULL-SCALE OFF OFF OFF OFF ON OFF OFF ON ON ON
2 3
BAR 3 BAR 2 BAR 1 BAR 0 B. DOT MODE
0.1f
EXTERNAL OSCILLATOR
1. INPUT = 0 BAR 4 OFF OFF OFF OFF ON
2. INPUT = 5% OF FULL-SCALE OFF OFF ON OFF OFF
A. SINGLE 9V SUPPLY VDD = 5V VDD 8 13 TC826 VSS 12 0. 1f
BAR 3 BAR 2 BAR 1 BAR 0
4 5 6 7
Figure 10. Display Option Formats
OSCILLATOR POWER SUPPLY
BAR Format
The TC826 power-ups in the BAR mode. BAR/DOT is pulled high internally. This display format is similar to a thermometer display. All bars/LCD segments, including zero, below the bar/LCD segment equaling the input signal level are on. A half-scale input signal, for example, would be displayed with BAR 0 to BAR 20 on.
B. DUAL SUPPLY
VSS = 5V
Figure 9. External Oscillator Connection
LCD Display Format
The input signal can be displayed in two formats (Figure 10). The BAR/DOT input (Pin 61) selects the format. The TC826 measurement cycle operates indentically for either mode.
DOT Format
By connecting BAR/DOT to VSS through a 1M resistor the DOT mode is selected. Only the BAR LCD segment equaling the input signal is on. The zero segment is on for zero input. This mode is useful for moving cursor or `needle' applications.
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A/D CONVERTER WITH BAR GRAPH DISPLAY OUTPUT TC826
LCD DISPLAYS
Most end products will use a custom LCD display for final production. Custom LCD displays are low cost and available from all manufacturers. The TC826 interfaces to non-multiplexed LCD displays. A backplane driver is included on chip. To speed initial evaluation and prototype work a standard TC826 LCD display is available from Varitronix. Varitronix Ltd. LCDs 4/F Liven House 61-63 King Yip Street Kwun Tong, Kowloon Hong Kong Tel: (852)2389-4317 Fax: (852)2343-9555 USA Office: VL Electronics / Varitronix 3250 Wilshire Blvd., Suite 901 Los Angeles, CA 90010 Tel: (213) 738-8700 Fax: (213) 738-5340 * Part No.: VBG-413-DP Other standard LCD displays suitable for development work are available in both linear and circular formats. One manufacturer is: UCE Inc. 24 Fitch Street Norwalk, CT 06855 Tel: 203/838-7509 * Part No. 5040: 50 segment circular display with 3 digit numeric scale. * Part No. 5020: 50 segment linear display.
LCD BACKPLANE DRIVER (PIN 15)
Additional drive electronics is not required to interface the TC826 to an LCD display. The TC826 has an on-chip backplane generator and driver. The backplane frequency is: FBP = FOSC/256 Figure 11 gives typical backplane driver rise/fall time versus backplane capacitance.
10 9 RISE/FALL TIME (X 100ns) 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 0 10 BACKPLANE CAPACITANCE (X 100pf) TA = 25C VS = 9V
Figure 11. Backplane Driver Rise/Fall Time vs. Capacitance
FLAT PACKAGE SOCKET
Sockets suitable for prototype work are available. A USA source is: Nepenthe Distribution 2471 East Bayshore, Suite 520 Palo Alto, CA 94303 Tel: 415/856-9332 Telex: 910/373-2060 `BQ' Socket Part No.: IC51-064-042 BQ
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TELCOM SEMICONDUCTOR, INC.

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